1. Field of the Invention
The present invention relates to a solid-state image pickup device and a method for driving the same. Particularly, the present invention relates to a solid-state image pickup device for converting analog signals output from unit pixels through column signal lines to digital signals and reading the digital signals, and to a method for driving the same.
2. Description of the Related Art
In recent years, a CMOS image sensor including a column-parallel ADCs (analog-digital converters) has been reported (e.g., see non-Patent Document 1: W. Yang et al., “An Integrated 800×600 CMOS Image System” ISS CC Digest of Technical Papers, pp. 304-305, February 1999). In this CMOS image sensor, ADCs are arranged for respective columns in matrix-patterned unit pixels.
FIG. 15 is a block diagram showing the configuration of a CMOS image sensor 100 including column-parallel ADCs according to a known art.
In FIG. 15, unit pixels 101, each including a photodiode and an intra-pixel amplifier, are two-dimensionally arranged in a matrix pattern so as to form a pixel array unit 102. In the matrix-pattern arrangement of the pixel array unit 102, row control lines 103 (103-1, 103-2, . . . ) are arranged for respective rows and column signal lines 104 (104-1, 104-2, . . . ) are arranged for respective columns. The row address and row scanning in the pixel array unit 102 is controlled by a row scanning circuit 105 through the row control lines 103-1, 103-2, . . . .
An ADC 106 is disposed at one end of each of the column signal lines 104-1, 104-2, . . . , so that a column processing unit (column-parallel ADC block) 107 is formed. Further, a digital-analog converter (hereinafter referred to as a DAC) 108 for generating a reference voltage Vref having a RAMP waveform and a counter 109 for measuring the time of a comparing operation in a comparator 110 (to be described later) by performing a counting operation in synchronization with a clock CK of a predetermined period are provided for the ADCs 106.
Each of the ADCs 106 includes the comparator 110 for comparing an analog signal obtained from the unit pixel 101 in a selected row among the row control lines 103-1, 103-2, . . . , through the column signal line 104-1, 104-2, or . . . , with a reference voltage Vref generated by the DAC 108; and a memory device 111 for holding the count value of the counter 109 in response to the output of the comparator 110. The ADC 106 has a function of converting an analog signal supplied from each unit pixel 101 to a digital signal of N bits.
Control of a column address and column scanning to each ADC 106 in the column processing unit 107 is performed by a column scanning circuit 112. That is, digital signals of N bits which have been AD converted by the ADCs 106 are sequentially read into a horizontal output line 113 having a width of 2N bits by column scanning of the column scanning circuit 112 and the signals are transmitted to a signal processing circuit 114 through the horizontal output line 113. The signal processing circuit 114 includes sensing circuits, subtraction circuits, and output circuits, the number thereof being 2N corresponding to the horizontal output line 113 having a width of 2N bits.
A timing control circuit 115 generates clock signals and timing signals required by the operations of the row scanning circuit 105, the ADCs 106, the DAC 108, the counter 109, and the column scanning circuit 112 based on a master clock MCK, and supplies the clock signals and timing signals to corresponding circuits.
Next, the operation of the CMOS image sensor 100 having the above-described configuration according to the known art will be described with reference to the timing chart shown in FIG. 16.
After a first reading operation from the unit pixels 101 of a selected row to the column signal lines 104-1, 104-2, . . . , has become stable, a reference voltage Vref of a ramp waveform is supplied from the DAC 108 to each of the comparators 110. Accordingly, the respective comparators 110 compare the signal voltage Vx of the column signal lines 104-1, 104-2, . . . , with the reference voltage Vref. In this comparing operation, the polarity of the output Vco of the comparator 110 is reversed when the reference voltage Vref and the signal voltage Vx become equal to each other. In response to the reversed output of the comparator 110, a count value N1 of the counter 109 according to the comparison time in the comparator 110 is stored in the memory device 111.
In the first reading operation, a reset component ΔV of each unit pixel 101 is read. The reset component ΔV includes fixed pattern noise as offset, which varies in each unit pixel 101. However, since the variation of the reset component ΔV is generally small and the reset level is common in all the pixels, the signal voltage Vx of the column signal lines 104 at the first reading operation is approximately known. Therefore, at the first operation of reading the reset component ΔV, the comparison time in the comparator 110 can be shortened by adjusting the reference voltage Vref of a ramp waveform. In the known art, the reset component ΔV is compared in a count period of 7 bits (128 clocks).
In a second reading operation, a signal component according to the amount of incident light in each unit pixel 101 is read in addition to the reset component ΔV in the same manner as in the first reading operation. That is, after the second reading operation from the unit pixels 101 in the selected row to the column signal lines 104-1, 104-2, . . . , has become stable, the reference voltage Vref of a ramp waveform is supplied from the DAC 108 to each of the comparators 110. Accordingly, the respective comparators 110 compare the signal voltage Vx of the corresponding column signal lines 104-1, 104-2, . . . , with the reference voltage Vref.
At the same time when the reference voltage Vref is supplied to the comparators 110, the counter 109 starts second counting. Then, in the second comparing operation, the polarity of the output Vco of the comparator 110 is reversed when the reference voltage Vref and the signal voltage Vx become equal to each other. In response to the reversed output of the comparator 110, a count value N2 of the counter 109 according to the comparison time in the comparator 110 is stored in the memory device 111. The first count value N1 and the second count value N2 are stored in different areas in the memory device 111.
After the above-described series of AD converting operations, the column scanning circuit 112 performs column scanning, whereby the first and second N-bit digital signals held in each memory device 111 are supplied to the signal processing circuit 114 through 2N lines of the horizontal output line 113. Then, the subtraction circuit (not shown) in the signal processing circuit 114 performs subtraction (second signal)−(first signal) and the result is output. Then, the same operation is sequentially performed for the other rows, so that a two-dimensional image is formed.
In the CMOS image sensor including column-parallel ADCs according to the known art, each memory device 111 must hold the first and second count values N1 and N2. Thus, 2N memory devices 111 are required for an N-bit signal, so that the scale and area of the circuitry increases. Further, N-series clocks CK1 to CKN must be input from the counter 109 to the memory devices 111, so that clock noise and power consumption increase. Further, 2N lines are required in the horizontal output line 113 in order to output the first and second count values N1 and N2, and the current increases accordingly. In addition, N subtraction circuits are required for subtraction of the first and second count values N1 and N2 before output, so that the scale and area of the circuitry increase.
In order to realize high-speed imaging, a frame rate is increased by skip-reading pixel information (e.g., see non-Patent Document 2: M. Loose et al., “⅔-inch CMOS Imaging Sensor for High Definition Television”, 2001, IEEE Workshop on CMOS and CCD Imaging sensors). By adopting this method, the frame rate of 60 frames per second can be realized in the interlaced scanning shown in FIG. 18, although the frame rate is 30 frames per second in the progressive scanning shown in FIG. 17. In other words, when pixel information to be output is read by skipping rows, for example, when the number of rows to be read is ½, the frame rate can be doubled.
However, in the known art described in non-Patent Document 2, that is, in the technique of increasing the frame rate by reading pixel information by skipping rows, the exposure time in each unit pixel is shortened as the frame rate increases. For example, the exposure time is reduced by half when the frame rate doubles. As a result, the effective sensitivity of the unit pixel is reduced by half. Therefore, when the frame rate is increased by applying skip reading of pixel information in the CMOS image sensor 100 including column-parallel ADCs, the sensitivity of the unit pixel decreases due to the higher frame rate, and thus the sensitivity of imaging result decreases disadvantageously.